Decreasing SoC Test Power Dissipation and Test Data Volume Based on Pattern Recombination

Abstract

Ever-growing test data volume and test power dissipation poses significant cost and security challenges in testing core-based system-on-chip (SoC). In this paper, a test pattern recombination technique is proposed to improve test data compression and decrease scan test power dissipation. The proposed technique first analyzes the entropy of a test set, which is used to determine the maximum compression ratio, and then divides the test set into a group of patterns that are used as scan slices for scan test based on multi-scan chains. The probability of the compatibility between the patterns in every vector is calculated, according to which the patterns of each test vector are recombined so that the patterns with high compatible probability are placed closely. Finally, for all the test vectors in a test set, a unified arrangement order for their patterns is determined based on the goal that the test set can be compressed and the scan test power dissipation can be decreased to advantage. The proposed scheme is applied to ISCAS89 test benchmarks and their MinTest test sets are used. The experimental results show that compared to the recently presented scheme, the proposed technique can effectively ensure a high data compression ratio and reduce shift power dissipation during testing.