Decoupling capacitor power ground via layout analysis for multi-layered PCB PDNs

Abstract

A modeling methodology to calculate the decoupling capacitor interconnect inductance in a multi-layer PCB is proposed herein. The methodology is based on the resonant cavity model of parallel planes. The self-inductance and mutual inductance are extracted to understand the via configuration influence on the effectiveness of decoupling capacitors. A special layout of decoupling capacitor is proposed to increase the effectiveness of the decoupling capacitors by taking maximum advantage of the mutual inductance between interconnect vias with two decoupling capacitors placed in a pair, and two pairs of power and ground vias placed in alternating directions as close as possible. The number of decoupling capacitors needed can be reduced dramatically. Three PCB PDN designs are used to present the effectiveness of doublet layout in different design scenarios. Similar analysis is extended to 3-terminal decoupling capacitor layout design. The decoupling capacitor interconnect inductance of the five via layouts for 3-terminal capacitors is analyzed. The number of decoupling capacitors needed for a commercial product using the doublet layout and 3-terminal capacitor layout is compared to the design with an alternating decoupling capacitor layout to reflect the impact of the decap layout design on the PCB PDN performance.