Deciphering the Growth Mechanism of Self-Assembled Nanowires on Pt-Deposited Ge(001) via Scanning Tunneling Microscopy and Density Functional Theory Calculations

Abstract

Shrinking the size of electronic components has been highly desirable in the semiconductor industry in recent years, and the next breakthrough in reducing the size of electronic devices may be via the bottom-up approach. Previous research showed that the deposition of metal atoms onto semiconductor surfaces could result in the self-assembly of atomically thin nanowires (NWs) extending for hundreds of nanometers. However, current understanding of the self-assembly mechanism of the NWs on semiconductor surfaces is still limited and unclear. Here, through a combination of scanning tunneling microscopy (STM) and density functional theory (DFT) calculation, the atomistic details of NWs growth on Pt-modified Ge(001) surfaces are uncovered. Directly observing the coexistence of various intermediate phases after Pt deposition enables us to explore the correlation among these phases, which provides important insights in deciphering the self-assembly mechanism of the NWs on semiconductor surfaces. Deposited Pt atoms are capable of chemically interacting with surface atoms on Ge(001) surface layer at elevated temperature (∼873 K) leading to the formation of various phases (e.g., α-terraces, β-terraces, and NWs). Among them, three-row-wide trench–plateau structures are clearly identified in this work, and an energetically favorable structure for this phase is unveiled using DFT calculations. It is found that this intermediate phase plays a critical role in the process of NWs growth, and the trenches on the edges are believed to be the cradle for NWs growth. The atomistic understanding of the self-assembly of nanostructure on Ge(001) surfaces could further help us design more complex nanostructures on semiconducting platforms, which is crucial for further reduction in the size of electronic devices.