Decimation Filter With Improved DC Biasing and Data Transfer

Abstract

Decimation filters are still the most complex and valuable superconductor digital circuits, so it is natural to use them to compare different design techniques. In the paper we discuss two new techniques. The first deals with the DC biasing scheme. For debugging purposes it is convenient to use separate power lines for different functional blocks. However, the lines occupy extra space, which could be unacceptable for a final design, when the decimation filters become part of larger circuits, for example, low-pass or band-pass ADCs. We will discuss an efficient rewiring technique that saves space during the connection of separate power lines after the circuit is debugged. The second technique is a selective use of micro-strip lines. Our solution contrasts with extreme recommendations for micro-strip lines as a universal tool for inter cell connections. More specifically for each connection we select either Josephson transmission or micro-strip line connection to keep the occupied area as small as possible. This highly custom design is possible due to parametric cell technique that dramatically accelerates the design procedure. In particular, we easily converted the circuit initially developed for 1 kA/cm2 standard HYPRES technology to the advanced technology with higher (4.5 kA/cm2 ) critical current density. The filter has 20 GHz and 40 GHz target sampling frequencies for 1 kA/cm2 and 4.5 kA/cm2 fabrication processes respectively. The circuits are fully operational at low frequency.