Abstract
A low-power, sparse-scan, readout architecture has been developed for the ATLAS pixel front-end electronics. The architecture supports a dual discriminator and extracts the time over threshold (TOT) information along with a 2-D spatial address of the hits and associates them with a unique 7-bit beam crossing number. The IC implements level-1 trigger filtering along with event building (grouping together all hits in a beam crossing) in the end of column (EOC) buffer. The events are transmitted over a 40 MHz serial data link with the protocol supporting buffer overflow handling by appending error flags to events. This mixed-mode full custom IC is implemented in 0.8 /spl mu/ HP process to meet the requirements for the pixel readout in the ATLAS inner detector. The circuits have been tested and the IC has been found to provide dead-time-less ambiguity-free readout at 40 MHz data rate.
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