Abstract
Fast and accurate monitoring of the phase, amplitude, and frequency of the grid voltage is essential for single-phase grid-connected converters. The presence of DC offset in the grid voltage is detrimental to not only grid synchronization but also the closed-loop stability of the grid-connected converters. In this paper, a new synchronization method to mitigate the effect of DC offset is presented using arbitrarily delayed signal cancelation (ADSC) in a second-order generalized integrator (SOGI) phase-locked loop (PLL). A frequency-fixed SOGI-based PLL (FFSOGI-PLL) is adopted to ensure better stability and to reduce the complexity compared with other SOGI-based PLLs. A small-signal model of the proposed PLL is derived for the systematic design of proportional-integral (PI) controller gains. The effects of frequency variation and ADSC on the proposed PLL are considered, and correction methods are adopted to accurately estimate grid information. The simulation results are presented, along with comparisons to other single-phase PLLs in terms of settling time, peak frequency, and phase error to validate the proposed PLL. The dynamic performance of the proposed PLL is also experimentally validated. Overall, the proposed PLL has the fastest transient response and better dynamic performance than the other PLLs for almost all performance indices, offering an improved solution for precise grid synchronization in single-phase applications.
Highlights
Renewable energy sources are integrated into the grid using grid-synchronized voltage source converters
This paper presents a new method for removing the DC offset effect from a grid synchronization unit using arbitrarily delayed signal cancelation (ADSC) in a SOGIPLL
Unlike other phase-locked loop (PLL) that rely on a second-order generalized integrator (SOGI), the proposed PLL can be accurately represented by a dominant second-order system, making the loop filter design process straightforward
Summary
Renewable energy sources are integrated into the grid using grid-synchronized voltage source converters. A mixed second-and third-order generalized integrator (MSTOGI)-based PLL is presented in [16, 17]; it contains an extra branch to the SOGI block to eliminate DC offset and high-frequency harmonics from input signals. The SOGI-FLL with fixed frequency proposed in [21] incorporates a low pass filter with notch characteristics and a linearized phase error compensation to mitigate the double-frequency oscillation in the estimated grid information This FLL has straightforward parameter tuning and selective harmonic rejection capability based on a linearized phase-loop transfer function, it has limited DC offset rejection capability. The effects of frequency variations and ADSC on the proposed PLL are considered, and phase and voltage amplitude correction methods are adopted to accurately estimate grid information. The derived small-signal model does not consider the dynamic of the phase offset error, so to enhance its accuracy, compensation for the phase offset error dynamic is calcu-
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