DC Modeling of Lateral High-Voltage MOSFETs for High-Voltage Integrated Circuits

Abstract

We have developed a physically based circuit-model of lateral high-voltage MOSFETs for design optimization of high-voltage integrated circuits (HVICs). The carrier density and the potential distribution in the channel surface and in the drift region depend on the structure of HV MOSFETs, such as the drift region and the field plate, and the voltage applied to the gate, the field plate, and the n drain. The developed DC model is comprised of five carrier-transport equations, one for the channel region and four for the drift region, which are the drift region overlapped with the gate, the drift region with a cylindrical junction, the drift region under the field plate, and the drift region without the field plate. The developed model is applicable to LDMOSFETs and EDMOSFETs, and the simulations with the model agree with the measurements for SOI EDMOSFETs within a tolerance of 3 %.