DC blocking via structure optimization and measurement correlation for SerDes channels

Abstract

SerDes (Serializer/DeSerializer) is widely used in gigabit Ethernet systems, fiber-optic communication systems, and storage applications for high-speed data transmission between different ASICs (application-specific integrated circuit) with the significant advantage of saving package pin numbers. The channel connecting the Serializer/DeSerializer in two different ASICs on a PCB (Printed Circuit Board) is the SerDes channel defined in the paper. Since DC biases in different ASICs are usually different for their Serializer/DeSerializer circuits, DC blocking capacitors are then necessary to block the DC path for signal transmission through the SerDes channel. It is known that the trace impedance on a PCB can be well controlled in manufacturing while it is difficult for a DC blocking via structure. Therefore, the blocking via structure is the main discontinuity contributor of the SerDes channel. In this paper, two different DC blocking via structures are studied. The performances of the two structures are compared and correlated up to 20 GHz with full-wave modelling and measurements. This study reveals the advantages/disadvantages of the two via blocking structures. A via optimization tool, which is based on the cavity resonance algorithm to speed up the optimization, is used to obtain the optimized parameters for the two blocking via structures, and the following full-wave simulations give further performance explorations of the two via structures.