DC bias effects on data retention at room temperature in SONOS nonvolatile memory devices

Abstract

This paper reports on a significant charge loss phenomenon at room temperature by a small DC bias applied to the gate of a SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) transistor, with a negative bias for program state (excess electrons) and a positive bias for erase state (excess holes). The decay rate of the program or erase threshold voltage is found to fit an exponential function of gate bias. This exponential bias dependence may be explained by Frenkel-Poole emission of trapped charge in the nitride layer. The charge decay by DC bias correlates with the data retention at elevated temperatures. The bias acceleration feature can be used as a quick room-temperature retention screen in place of the conventional and more time-consuming high-temperature screen, particularly for wafer-level sampling. The results explain the gate read disturbance and suggests the gate bias for read operation to be set around 0 V for minimum read disturbance.