DC and RF Performance Optimization of Strained Si/Si1-xGex Heterojunction SOI P-TFET

Abstract

This paper proposes DC and RF performance optimization of single gate strain Si/Si 1-x Ge x P- channel gatedrain underlap Tunnel Field Effect Transistor (TFET) using 2D TCAD simulation tool. Here, in the heterodielectric gate structure, the I ON current is improved by effectively situating the gate over the source edge. Gate-drain underlap structure provides reduced ambipolar conduction in the proposed P- channel Tunnel Field Effect Transistor (P-TFET) device. The proposed device demonstrates great execution with an I ON /I OFF of 1014 and average subthreshold swing (SS) of 53mV/dec. In addition, we have also optimized analog/RF figure of merit characteristics such as parasitic capacitances, transconductance, and transit frequency of the proposed Heterojunction SOI P-TFET (HJ-SOI P-TFET).