Abstract
Accurate prediction of voltage variation due to IR drop becomes increasingly important in performance driven system board design as supply voltages continue to reduce while current requirements keep on increasing. With advantages of user-friendly and powerful commercial simulation tools nowadays, accurate extraction of power plane resistance is realized even in today system board designed with complex metallization structures due to dense clusters of via holes and cutouts in power and ground planes. As a fundamental electrical requirement in board design, post-layout simulation for DC analysis is proven to be an essential step that benefits the board development productivity and design validation. Board design trade-off and optimization such as copper thickness and number of layers for power planes, static current crowding hot spots prediction and power/ground via population are also discussed in this paper.
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