Abstract
This paper presents the design of a balanced power amplifier (PA) using a 130-nm SiGe BiCMOS process. The PA consists of three stages, each based on cascode topology. The design of the PA was optimized using low-Q matching networks for the D-band applications. The results based on EM-simulation of the PA, with assistance of vbic and hicum models for the transistor, demonstrate an average peak gain of 26.5 dB with the 3-dB bandwidth higher than 80 GHz. In terms of large-signal, the PA provides an output power and PAE larger than 14 dBm, and 4 percent, respectively, in the D-band. Moreover, it provides an output power greater than 13 dBm at 110–190 GHz. The PA is highly suitable to drive frequency multipliers for the development of broadband sub-THz signal sources. The future work includes measurement of the PA.
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