Data-Space Relocation to Improve Data Cache Performance for Embedded Multi-threaded Processor Systems

Abstract

Multi-threaded processor execution is a design strategy for performance improvement and energy reduction. With the multi-threaded execution, the processor's idle time of one thread can be hidden by executing other threads so that the overall execution time can be reduced. One typical issue with the multi-threaded processor design is cache. Cache reduces long and power-consuming memory accesses, and has become an essential component in the modern processor system. However, multi-threaded execution can interfere the cache access behavior, potentially causing more cache misses and leading to degraded cache (hence system) performance. This paper presents an off-line thread data-space relocation approach to reduce such cache misses. The approach does not introduce any performance or hardware overhead. The experiments on a set of applications show that with our approach, an average of 13.47% data cache misses can be reduced, and 10.23% performance improvement and 10.91% energy saving can be achieved.