Abstract
An extension to the cycle-static dataflow graph model is proposed. It is based on the insight that in current digital signal processing (DSP) applications a significant amount of time and resources is spend on the routing of the data between the processing operations. If this part of the application is do be synthesized from a specification to a software or a hardware realization both automatically and efficiently, a systematic approach is to be taken for that data routing. The new model fits in GRAPE, an environment for the fast prototyping DSP systems on arbitrary target architectures, consisting of programmable DSP processors and FPGAs. Besides the definition of the model, the authors present some clarifying examples. They discuss the code generation of data-routing specifications for a specific synthesis path. Finally, a larger example and its implementation validate the model.
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