Data retention prediction for modern floating gate non-volatile memories

Abstract

Extensive gate stress measurements after cycling on test structures and on products have been carried out on EEPROMS. The leakage current in the worst case SILC cell has been measured at very low electrical field (down to 1 MV/cm), and has been fitted with various formulae like Fowler-Nordheim (FN), Poole-Frenkel (PF), trap-assisted tunneling (TAT) and hopping conduction model (HCM). In such EEPROMS, a strong asymmetry of SILC has been found. The SILC at low-Vt state is worse than that at high-Vt state. The effect of pulse shaping on suppressing SILC is also demonstrated. A new method is reported to perform data retention estimation and product reliability based on field accelerated tests (gate stress tests). The data retention time of the SILC cell has been determined based on the worst case data from gate stress experiments. The new method can be applied to other floating gate non-volatile memories, such as flash.