Abstract
Scalable interconnect network for both global and local for data reordering and its implementation are presented in this paper. These networks were implemented for Fast Fourier Transform (FFT) and Discrete Cosine Transform (DCT). The number of processing elements (PE) can be reduced significantly using partial column structure to compute the transforms. This makes it suitable for usage in handheld devices. Data reordering is required between stages (columns). The structure will reorder data on the fly without the need for storage elements. Scalability of the network is based on the transform size and the number of processing elements (PE) in each processing column. The structure can be used as a tool to evaluate throughput vs. complexity (cost and area) of the overall system prior to design commit. A first order of hardware cost analysis is also presented.
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