Abstract
The goal of the paper is to present the ideal form of an NDN forwarding engine on a commercial off-the-shelf (COTS) computer. In this paper, we design a reference forwarding engine by selecting well-established high-speed techniques and then analyze a state-of-the-art prototype implementation to identify its performance bottleneck. The microarchitectural analysis at the level of CPU pipelines and instructions reveals that dynamic random access memory (DRAM) access latency is one of bottlenecks for high-speed forwarding engines. Based on the analysis result, we design two prefetch-friendly packet processing techniques to hide DRAM access latency. The prototype employing the techniques achieves a forwarding rate exceeding 40 million packets per second on a COTS computer.
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