Data Persistence

Abstract

In a system with volatile hardware components (like CPU registers, processor caches, etc.), simply issuing a store operation does not guarantee that the update is durably written to PM. For instance, when a store operation is issued by the CPU, modern processors perform the update to a write-back cache. The write-back cache then lazily drains the update to PM, for example, when a cache line conflict occurs. Any subsequent failure erases the volatile write-back cache (or generally, any volatile component) and the update is lost. To prevent data loss on failure, hardware systems must guarantee that the updates reach PM.