Abstract
As the advances in hardware technology, the gap between fast CPU and the slow memory system is increased severely also in sequential computer systems. Hierarchical memory systems are used in sequential computers to bridge the gap. Cache is a widely used mechanism in the memory hierarchy. But it has been found that cache performance is not satisfying for many important application algorithms since its hit ratio is very low for many frequently data access patterns due to conflict use of the cache lines. This problem shares some similarity with the problem of memory module access conflict in parallel memory systems discussed in Chapter 10. In addition, some special issue (data reuse rate) need to be considerate in cache systems. We will discuss the cache line conflict problem and some techniques to solve it in this chapter.
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