Abstract

The Belle II experiment is a new generation B-factory experiment at the upgraded accelerator SuperKEKB. The luminosity of the accelerator is expected to be more than 40 times higher than that of the previous KEKB, and the average Level 1 trigger rate is estimated to become up to 30 kHz with a total raw data size of ~ 1.1 Mbytes resulting in a data throughput of ≥ 30 Gbytes/sec. In order to manage this huge data flow, the Belle II DAQ system is designed to perform a multi-step data reduction using a large number of CPUs implemented in various DAQ components from the detector readout modules to the High Level Trigger farm. In this article, the design of the data flow and the architecture of the High Level Trigger farm in the Belle II DAQ system is reported.

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