Abstract

The ΔΣ type data converters are widely used in audio signal conditioning system and other low frequency signal acquisition systems in which large dynamic range signal conditioning is required. With the progress of CMOS technology, supply voltage continuously scales down with the feature size. The international technology roadmap for semiconductor (ITRS) shows that the operating supply voltage for CMOS transistors is 1-V currently and approaches to 0.6-V until 2020. The purpose for supply reduction is to prevent device from breaking down, because the gate oxide is becoming thinner and thinner. The ΔΣ-ADC can convert analog signal into their high precision digital representations. Amplifier is the key building block and its noise as well as linearity limits the overall ADC performance. Low supply voltage results into small voltage headroom and swing for amplifier which may deteriorate dynamic range and cause unacceptable harmonic distortion. To overcome the above problems usually large power is needed. In this chapter, design of ΔΣ-ADC under only 1-V supply is explored. Various techniques are adopted to achieve high resolution under low voltage while keeping the power dissipation under a low level. The function of a ΔΣ-DAC is to reconstruct the analog signal and deliver enough power to the output load. Taking the digital hearing aid as an example, if large sound level is required, the peak output power can exceed tens of mill watts, which is an order larger than all circuits excluding the DAC. Hence more accurately speaking, low power DAC means that power delivery efficiency of the DAC is high. Adoption of class-D amplifier is a good way to achieve good efficiency. However fast switching operation may introduce extra noise and distortions, dedicated techniques should be employed.

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