Dark Silicon Patterning: Efficient Power Utilization Through Run-Time Mapping

Abstract

An efficient run-time application mapping approach can considerably enhance resource utilization and mitigate the dark silicon phenomenon. In this chapter, we present a dark silicon aware run-time application mapping approach that patterns active cores alongside the inactive cores in order to evenly distribute power density across the chip. This approach leverages dark silicon to balance the temperature of active cores to provide higher power budget and better resource utilization, within a safe peak operating temperature. In contrast to exhaustive search based mapping techniques, the proposed agile heuristic approach has a negligible run-time overhead. This patterning strategy yields a surplus power budget of up to 17 % along with an improved throughput of up to 21 % in comparison with other state-of-the-art run-time mapping strategies, while the surplus budget is as high as 40 % compared to worst case scenarios.