Abstract
Both IMP TaN and CVD TiN barriers have been shown to be excellent materials against copper diffusion using etch-pit, bias-thermal-stress (BTS) or C(V) tests on planar structures. These results however cannot account for the real barrier thickness and stoichiometry when deposited in damascene features. Such information is critical for advanced technologies exploiting high aspect ratio design rules. Via structures, 0.32 and 0.26 μm in diameter and 1 μm deep, etched through SiO 2 down to bare silicon, are combined with a standard etch-pit test to look for the formation of copper silicide as a function of barrier material and process conditions. Using these test-structures it was shown that the CVD process would be mandatory to maintain the required copper barrier performance in sub-quarter micron technology.
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