DAM: Deadblock Aware Migration Techniques for STT-RAM-Based Hybrid Caches

Abstract

Last Level Caches (LLCs) play a critical role in reducing the number of costly off-chip memory accesses. Hence, there is a demand to make the LLCs larger to meet the requirements of growing dataset size of emerging data-intensive applications. Non-volatile STT-RAM-based caches with high memory density are a promising alternative to satisfy such a demand. However, STT-RAM-based caches have high write-latency and write energy. Therefore, researchers proposed a unified cache consisting of both SRAM and STT-RAM portions to handle expensive writes in these large hybrid LLCs. However, these large LRU-managed LLCs still remain underutilized due to the presence of a significant fraction of deadblocks (zero-reuse blocks) in them. By choosing the deadblock as an eviction candidate, we show a significant reduction in the LLC misses. Our work considers the entire set of the hybrid cache to select the deadblock as an eviction candidate. Therefore, we propose Deadblock-based Victim Selection (DVS), a deadblock-aware replacement policy. We observe that in up to 40 percent of cases, evicting a deadblock on an LLC miss requires migration of a cache block within the cache set. To incorporate this opportunity into DVS, we augment it with a cache block migration strategy and propose Deadblock-based Migration (DM) policy. The detailed evaluation on the SPEC CPU2006 workloads shows that DVS and DM enhance the performance of the system by up to 13 and 52 percent, respectively. Our results demonstrate that a cache replacement policy that is both deadblock-aware and migration-aware is essential in improving the performance of large hybrid LLCs.