Abstract
This paper presents the design language DALLAS set up for the development of a control unit of a processor implemented in a single VLSI whose size is approximately 200,000 transistors. The processor is a finite state machine and its control unit (70% of the silicon area) has a very large AND-OR network implemented with PLA's. Within the present tool, processor control and operation functions are specified in a powerful high level language, validated and translated into boolean logic and then submitted to boolean minimization. With regard to PLA implementation on silicon, efficient topological minimization is achieved by means of a special folding technique optimized to the specific finite state machine matrix morphology. A 30% reduction of the PLA's active area has been obtained with obvious benefits both in yields and performance.
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