Cyclic process nets as a high-level behavioral specification model for embedded systems synthesis

Abstract

High-level specifications of the behavior of information processing systems consist of data and control flow descriptions as well as of timing requirements to be met by a feasible implementation. These requirements are in general captured as bounds on the processing times of periodic and aperiodic computational tasks. Cyclic process nets are introduced as a high-level computational model for representing both flow information and timing bounds of information processing systems. Different iteration and varying computation times which are characteristic for HW/SW implementations in embedded systems, combined with the associated functional description yield then a high-level behavioral specification of such systems. As a main result, the presented scheduling algorithm detects hidden time intervals in the specification which may then be exploited as a resource for HW/SW partitioning purposes during design space exploration. Thus, the proposed cyclic process nets form a foundation for codesign tasks in embedded systems synthesis. Finally, the resulting design flow is discussed by means of an application example.