Cycle decomposition in NCL

Abstract

In null convention logic (NCL) circuits, cycles are the fundamental unit of data storage, roughly equivalent to combinational logic bounded by latches in clocked design. Implementing the various tools common to IC design flows, such as static timing analysis and scan insertion, requires accurately identifying these cycles. Threshold gates are the basic building blocks of NCL cycles. To date, mechanisms for automatically identifying relevant NCL circuit cycles have been lacking. The NCL analyzer solves the problem of automatically identifying cycles from a gate-level netlist. It does this by identifying the acknowledge signal feeding a register from its relative signal polarity and then finding the intersection of a forward and reverse circuit traversal. Although the NCL analyzer is currently a stand-alone tool, we expect it will become an integral part of nearly all NCL-specific tools - including static timing analysis, orphan checking, ATPG, and possibly synthesis.