Abstract
AbstractIn this paper, we present CVD (Chemical Vapor Deposition) growth and passivation of tungsten (W) and titanium nitride (TiN) nanocrystals (NCs) on silicon dioxide and silicon nitride for use as charge trapping layer in floating gate memory devices. NCs are deposited in an 8 inches industrial CVD Centura tool. W and TiN are chosen for being compatible with MOSFET memory fabrication process. For protecting NCs from oxidation, a silicon shell is selectively deposited on them. Moreover, for a better passivation, TiN NCs are encapsulated in silicon nitride (Si3N4) in order to get rid of oxidation issues. After high temperature annealing (1050°C under N2 during 1 minute) XPS measurements point out that NCs are still metallic, which makes them good candidates for being used as charge trapping layer in floating gate memories.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
