溶液気化CVD法による(Ba, Sr) TiO<sub>3</sub>高誘電率薄膜形成

Abstract

High dielectric constant (Ba, Sr) TiO3 [BST] films have been deposited by liquid source chemical vapor deposition (CVD) method. The system consisted of a single-wafer, low-pressure thermal CVD reactor, a vaporizer for liquid source materials, and a shower-type gas nozzle head, giving stable BST film deposition on a 6-in. -diam substrate with uniform thickness and uniform chemical composition ratio. The source materials employed were Ba(DPM)2, Sr(DPM)2, and TiO(DPM)2 dissolved in tetrahydrofuran (THF), resulting in a conformal step coverage of BST films at lowered substrate temperatures, where DPM denotes dipivaloylmethanato. Moreover, the two-step deposition technique was developed to restrain protrusions formed on BST film surfaces at low temperatures, where BST films consisted of a buffer layer and a main layer; the buffer layer was an about 60-Å-thick layer of CVD-BST films annealed in N2 ambience. Thus, the two-step CVD deposition of BST films on Pt and Ru electrodes achieved an equivalent SiO2 thickness of teq_??_0.5nm, a leakage current of JL_??_1.0×10-8A/cm2 (at+1.1V) and a dielectric loss of tan δ_??_0.01 at a total film thickness of 250Å, along with a comformal coverage of 80% for a trench of an aspect ratio of 0.65. Then, for BST films deposited on patterned electrodes 0.24μm wide, 0.60μm deep, and 0.15μm high (each spaced by 0.14μm), the capacitance was demonstrated to be increased without a significant deterioration of the leakage current: the capacitance was measured to be increased in comparison with that for films on flat electrodes, by a factor corresponding to an increase in surface area due to sidewalls of storage-node-like pattern features. This capacitance increase reflects the most characteristic advantage of CVD, or an excellent step coverage on microscopic pattern features. These electrical properties obtained satisfy specifications of a capacitor for Gb-scale dynamic random access memories (DRAMS), giving a storage capacitance of more than 25fF/cell for a stacked capacitor having a storage node 0.2_??_0.3μm high.