CV characteristics of polycrystalline sige films with low GE concentration

Abstract

SiGe alloys are currently used for HBT and MOS as epitaxial layers for base or strained channel, respectively. In the poly phase, SiGe has been studied as a replacement for poly-Si in MOS gates due to its lower thermal budget and gate depletion and also due to the Workfunction Engineering for Vt adjustments. However, for application to CMOS technology as poly-SiGe gates, others constrains emerge such as quality of the oxide interface and etch chemistry. For both applications, the Ge fraction normally lies between 20% and 40%. In this study, authors use a low Ge contents (1%) poly-SiGe thin films aiming for MOS gate electrode. The Ge fraction was determined by RBS analysis. 230nm thick samples were deposited onto 10nm thermally oxidized 〈100〉, p-type Si substrates using silane and germane. Films were deposited in the temperature of 500°C and total pressure of 667Pa (5Torr) by vertical LPCVD. The samples were doped using 31P+ ion implantation from 5×1014cm−2 up to 2×1016cm−2 and annealed by RTP (40s) from 500°C up to 900°C. Rs values were obtained by 4-point probe technique and CV curves were extracted from nMOS capacitors with 200μm diameter. The same processing steps were used to fabricate similar poly-Si samples and capacitors for comparison.The poly-SiGe samples presented Rs values one order of magnitude lower than poly-Si and CV analysis of nMOS capacitors showed very good characteristics. The 1% Ge in the alloy ensures a low thermal budget for the overall process. Although a relatively high annealing temperature (800°C) must be used to reduce oxide charge and interface traps, the temperature is well below the necessary for poly-Si processing and can allow formation of the shallow junctions needed for next technological nodes.