Custom Instructions for Networked Processor Templates

Abstract

As Field-programmable Gate Arrays (FPGAs) continue to increase in size and capability, there is an increasing need to develop performant designs in good time. Networked processor templates support scalable on-chip parallelism while avoiding the complexity and long run time of FPGA synthesis tools. The performance of the resulting designs can be further enhanced by adding custom instructions to processors in the network. We show how to systematically choose parts of a design to implement as custom instructions. We illustrate the use of performance and area models targeting a particular networked processor template to explore design trade-offs. Various applications, such as N-body simulation and dissipative particle dynamics, demonstrate how hardware acceleration based on custom instructions can target state-of-the-art FPGAs.