Custom designed CPU architecture based on a hardware scheduler and independent pipeline registers — Concept and theory of operation

Abstract

System response time is a key element in hard real time systems. In classical Real Time Operating Systems (RTOS) based on software schedulers, overhead and jitter are a major problem when the number of tasks and the rate of context switches are high. Increased values for those parameters over admissible values can lead to performance degradation, increased power consumption or even deadline misses. If a part of the scheduling components or the entire functionality is moved from software to hardware, a significant improvement in task switching times can be achieved. This paper presents a custom designed multi pipeline register architecture (MPRA) that has a dedicated hardware scheduler unit integrated into the CPU.