Current Harmonics Dead Time Design Method to Achieve ZVS with Non-Linear Output Capacitance

Abstract

A novel current harmonic dead time design method is presented to guarantee zero-volt switching (ZVS) of a resonant LCCL network, regardless of loading condition, accounting for non-linear characteristics of the parasitic output capacitance. Dead time voltage modeling is omitted; an upper bound on necessary dead time to achieve ZVS is instead developed with a charge-based approach to modeling parasitic capacitance. The harmonic dead time design method is shown to conservatively estimate the necessary dead time, using only the harmonics created by all full-bridge inverters. The calculated dead time criterion is shown to be conservative for many loading conditions. Considerations are made for a mistuned systems and parasitic effects. Simulation validation of the design method is presented. A full hardware test also demonstrates the validity of the design technique. The harmonic design method can be applied to nearly any LCCL resonant converter designs to guarantee ZVS at all load conditions.