Current dynamics-based macro-model for power simulation in a complex VLIW DSP processor

Abstract

A methodology and a macro-modelling approach are presented for analysing low-level current dynamics at the instruction and program level for a complex VLIW DSP processor core. An instruction-level macro-model, whose input parameters can be extracted from the DSP core's assembly level program, is introduced for power modelling. For the first time, dynamic power models of algorithms are introduced and verified with real power measurements of a DSP processor core in a VLSI chip. Results from both cryptographic and bubble sort applications show that dynamic power can be modelled with an average error in energy estimation ranging from 0.3% to 9.7%. The instruction-level macro-model of power also supports different clock frequencies and compressed algorithmic traces, important for security aware compilers. In general, the research is important for analysing and modelling the impact of software on power, the design of embedded cryptographic VLSI systems that are safe from power attacks, and for reliable design by detecting the peak current values generated by the software application.