Current-Bunch Concept for Parasitic-Oriented Extraction and Optimization of Multichip SiC Power Module

Abstract

Parasitic inductance reduction is increasingly vital for the SiC power module in high-frequency and high-capacity applications. To address the parasitic issue, the automatic layout design offers the potential to pursue the optimal configuration of the power packaging. However, the efficient and accurate parasitic extraction of the packaging is the bottleneck of the automatic design scenario. In this letter, the current-bunch concept is proposed to achieve a tradeoff between the efficiency and accuracy of the parasitic extraction. The mathematical models are created to estimate the parasitics by using the proposed concept. Additionally, the challenge of abundant mutual-inductance caused by the multiplied power chips in the SiC power module is highlighted. Simulation and experimental results further demonstrate the advantages of the current-bunch concept. With the aid of the proposed approach, the packaging layout of a multichip SiC power module is optimized, and the parasitic inductance is reduced by 29.2%.