Abstract
Through Silicon Via (TSV) is now becoming one of the most critical and enabling technologies for 3-D integration.Vertical interconnection of several chips offered by TSV will result in improved performance and functionality, miniaturization in size and weight and reduced power consumption. Cu as TSV filling material is well used in the traditional damascene process. In this work, Cu seed deposition in high aspect ratio features using traditional PVD tool is developed and seamless TSV Cu filling is achieved. The TSV via dishing in Cu CMP soft landing step is also discussed. Finally, the TSV via resistance is extracted from the special designed test structure without additional bonding wafer or backside patterning.
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