Abstract
Wafer-to-wafer (W2W) hybrid bonding is a key process technology in advance heterogeneous integration. Electrical connections between top surface metal lines of different wafers (e.g. memory, logic) can be made by means of wafer-to-wafer stacking to enable reduced latency and data-bandwidth between different wafers.Successful implementation of this key process technology requires good bonding interfaces with controlled surface roughness and precise control of dishing/protrusion on both the dielectric and Cu pad surfaces.This paper characterizes the chemical mechanical planarization (CMP) process on hybrid bonding Cu surfaces for different Cu pad designs. It provides the guidelines in design of Cu pad/spacing, line/spacing pattern to achieve desired bonding surfaces after CMP polishing. This simplifies the layout design and reduces the process tuning cost.
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