CSI-SRAM: Design of CMOS Schmitt trigger inverter based SRAM cell for low power applications

Abstract

In modern digital systems, as the number of transistors is increasing; the power consumption has been increasing tremendously. To reduce the power consumption, we can consider multiple supply voltages. In this paper, we propose the radiation-hardened Static Random Access Memory (SRAM) bit cell targeted at low-voltage functionality, while maintaining high soft-error robustness. The proposed SRAM employs a novel dual-driven separated-feedback mechanism with multiple supply voltages to tolerate upsets with charge deposits at a scaled 500-mV supply voltage. In this paper, a novel modified Static Random Access Memory (SRAM) cell based CMOS Schmitt trigger inverter designed for memory architectures which maintain high soft-error robustness is proposed. The Stability of CMOS Schmitt trigger inverter is more compared to basic CMOS inverter. The Proposed SRAM cell reduces delay by 65–70% and power by 80–85% and increases read stability by 60–70% compared to 13T SRAM cell based memory architecture. Results have been verified by 45nm CMOS technology in Cadence using virtuoso.