μc-Si thin film transistors with very thin active layer

Abstract

N-type microcrystalline silicon (μc-Si) top-gate Thin Film Transistors (TFTs) are fabricated at a maximum temperature of 180°C using different thicknesses of undoped μc-Si active layers. The effect of the thickness on the TFT performance is experimentally studied and then modeled using Silvaco software tools. The experimental high improvement of the subthreshold swing and the limitation of the rear channel effect, when using very thin active layer, are shown to be due to the increase of the lateral electrical field between the source or drain and the active layer. This increase of the lateral field is shown to be much more important for defected active layer as the microcrystalline silicon one compared to single crystalline silicon active layer. The importance of the use of very thin active layer for amorphous or ploy–micro–nano-crystalline silicon based TFTs is then demonstrated.