Cryo-TRAM: Gated Thyristor based Capacitor-less DRAM for Cryogenic Computing

Abstract

Recent advancements in cryogenic quantum computing technologies offer the promise to provide an exponential speedup for certain compute applications. Due to large number of arbitrary rotations required in a quantum algorithm and continuous error correction to preserve the data integrity, it requires extensive memory and bandwidth [1]. Using DRAM as main memory operational at 77K [1], can keep the cooling cost low while still providing significantly lower leakage along with larger capacity. Thanks to the denser bitcell footprint compared to the 1T-1C DRAM cells, capacitor-less single transistor DRAM (1T-DRAM) devices have been explored to construct scalable memory systems for cryogenic applications. Lowering the temperature improves the retention time of the 1 T DRAM cells by reducing the generation and recombination of carriers, a major retention failure mechanism of the 1 T DRAM cells [2] at higher temperatures. Recently, a cryogenic 1 T-DRAM cell has been demonstrated using a partially depleted silicon-on-insulator (PDSOI) n-MOSFET with a floating body [3]. However, the reported narrow cell current margin results in a slow read operation and quasi-destructive read operation can impact endurance. Since the impact ionization or GIDL effect is the major write mechanism for the cell, reported write speed is also slow (> 10ns). Capacitor-less DRAMs based on Thin Capacitively Coupled Thyristor (TCCT) benefits from a very large Ion/off current ratio (> 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7</sup> ) and a non-destructive read that enable a fast read/write speed (<2 ns) [4], [5]. A novel Floating Body Diode (FBD) memory was proposed [6] by Intel, which builds upon the same gated thyristor principle of operation in a FinFET form-factor making it scalable as well as a lower voltage memory. These unique features can enable a simple, logic compatible, high speed, and high density memory for cryogenic applications. However, device-circuit optimization studies of TCCT DRAMs specifically for cryogenic applications have been rather limited. In this paper, through TCAD simulations, a thyristor RAM (TRAM) is demonstrated for cryogenic applications for the first time.