Cryogenic Response of HKMG MOSFETs for Quantum Computing Systems

Abstract

Hardware implementation of Quantum Processors require monolithic integration of CMOS controller and read-out interface circuits, operating at cryogenic temperatures (1-6K), to enable scale-up of the number of Q-bits and energy-efficient noise-tolerant circuit operation [1] (Fig. 1a). In this work, we investigate the critical role of interface traps near band-edge that affect both the sub-threshold swing (SS) and threshold voltage ( $(\mathrm{V}_{\mathrm{TH}})$ ) of high-K metal-gate (HKMG) n-channel MOSFETs at cryogenic temperature. We highlight two fundamental mechanisms that contribute to an increase in interface trap capacitance $(C_{\mathrm{it}})$ that affect both the SS and $(\mathrm{V}_{\mathrm{TH}})$ at cryogenic temperatures: (a) the proximity of the surface Fermi-level $(\mathrm{E}_{\mathrm{F}})$ to the edge of the conduction band $(\mathrm{E}_{\mathrm{C}})$ , where the density of interface traps $(D_{\mathrm{it}})$ is higher, and (b) higher sensitivity of the interface trap response for a given change in $\mathrm{E}_{\mathrm{F}}$ (Fig. 1b). We developed a physics-based cryo-CMOS transistor model [2], by incorporating multiple discrete interface traps located near $\mathrm{H}_{\mathrm{C}}$ and show excellent agreement with the experiments. This provides an important step towards optimization of future cryo-CMOS technology necessary for interface circuits in quantum processors.