Cryogenic MOSFET kink effect abatement

Abstract

The increasing interest in nanoelectronic devices that require cryogenic temperatures to function has lead ?to an increased need for analog CMOS circuits that can perform at these low temperatures. Conventional CMOS transistors, when operated at temperatures at which the majority of carriers experience freeze-out, exhibit an effect known as the kink effect. This occurs when holes generated by avalanche multiplication at the channel-drain interface become trapped in the channel region, causing a lowering of the threshold voltage of the device. We examine two methods of kink effect elimination in n-MOS transistors, one requiring epitaxial growth, and one utilizing retrograde well doping of a bulk substrate. The use of lightly p-doped epitaxial layers of silicon over a substrate of degenerately p-doped silicon to eliminate the kink effect in n-MOS devices was proposed by Broadbent. By providing a negatively biased, degenerately doped substrate that does not succumb to freeze-out we create a path for positively-charged holes to be drawn away from the channel region. We are simulating and fabricating n-MOS transistors to further examine this technique. 1 D-Poisson and 2D SSUPREM simulations have been run for n-MOS transistors fabricated on lightly doped p-epitaxial layers grown on degenerately p-doped silicon substrates. Variations in epitaxial layer thickness and substrate bias are considered. N-MOS transistors with gate lengths of 1.5 ?m to 4 ?m are currently being fabricated on p+ substrates with epitaxial layers ranging from 500 nm to 3 ?m in thickness. These devices utilize a backside contact to provide a variety of negative biases to the body of the n-MOS transistors. A range of bias values will be tested to examine the effect of increased substrate bias on device threshold and kink effect abatement. Fig. 1 shows the band diagram of the nMOS transistors under the gate stack for epitaxial layer thicknesses ranging from 1 ?m to 2.5 ?m. The transistors are shown following the patterning and etching of the polysilicon gate layer.