Cross-Talk Delay Fault Test Generation

Abstract

As design trends move toward nanometer technology, new Automatic Test Pattern Generation (ATPG) problems are emerging. During design validation, the effect of cross talk on reliability and performance cannot be ignored. So, new ATPG Techniques have to be developed for testing cross-talk faults that affect the timing behavior of circuits. Further, periodic testing of VLSI circuits can cause generation of excessive heat that can damage the chips under test. Therefore, it is much necessary to reduce the power dissipation during the testing phase also. This chapter deals with two multi-objective genetic-algorithms-based ATPGs, namely, Weighted Sum Genetic Algorithm (WSGA)-based ATPG and Nondominated Sorting Genetic Algorithm (NSGA-II)-based ATPG that generates test pattern set that has high fault coverage and low power consumption. Redundancy is introduced in NSGA-II-based ATPG by modifying the fault-dropping phase and hence very good reductions in transition activity are achieved. Tests are generated for scan versions of ISCAS’89, ISCAS’85, and ITC’99 benchmark circuits. Experimental results demonstrate that NSGA-II-based fault simulator gives higher fault coverage, reduced transitions, and compact test vectors for most of the benchmark circuits when compared with those generated by Weighted Sum Genetic Algorithm (WSGA).