Abstract
This study presents a method of extracting 3D metrological information for etched gate structures from top-down SEM images for use in critical dimension analysis. The variations in sidewall angle and bottom corner roundness are quantified as feature indices by multiple parameter profile characterization (MPPC), and are used as the main indicators of device performance. A stable algorithm developed based on simulation and experimental results partitions the SEM image signal into the sidewall and footing based on the first derivative of the image signal. The width of the sidwall is used as an index of the sidewall angle, and the width of the footing is used as an index of the footing roundness. The validity of the MPPC method is confirmed through experiments using actual poly-Si gate wafers, and is shown to have a 3σ accuracy of ±0.9° for sidewall angles deviating by mroe than 2°. The sidewall angle index and its distribution map are useful for evaluating the etching process, and are particularly effective for revealing subtle macro variations like asymmetry, while the footing roundness index is useful for screening out bad wafers. As MPPC employs only top-down SEM images, no throughput loss will be incurred in comparison with conventional CD measurements.
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