Cross-Layer Approaches to Designing Reliable Systems Using Unreliable Chips

Abstract

The design for manufacturing and yield (DFM&Y) is fast becoming an indispensable consideration in today's SoCs. Most current flows only consider manufacturability and yield at the lowest levels: process, layout and circuit. As such, these metrics are treated as an afterthought. With advanced process nodes, it has become increasingly expensive-and soon prohibitive-to guarantee bit level error free chips. The challenge now is to design reliable systems using chips that may have some faults. This has lead to approaches that consider DFM&Y at the system level where more benefit can be reaped, and to consider the problem across the design layers. This tutorial covers cross layer approach to design for DFM&Y spanning from the application all the way to manufacturing, overviews various techniques being explored today, and demonstrates its effectiveness on key applications including wireless, multimedia and imaging. We believe that this tutorial will benefit a large percentage of the attendees at VLSI Design 2008, and should elicit an excellent response at the VLSI Design 2008 conference, he tutorial is intended for application designers, chip architects, managers, CAD tool developers, researchers and students interested in System-on-Chip design, platform-based design methodologies, and trends in design for manufacturing and yield at the system level. Attendees should have basic (undergraduate-level) knowledge of VLSI Design and SoC design flows. Familiarity with architectural concepts such as IP based design, and applications such as wireless and multimedia is desirable, but not required. No specific knowledge of CAD tools or modeling languages is required for this tutorial.