Cross-cell interference variability aware model of fully planar NAND Flash memory including line edge roughness

Abstract

The main reliability issue of highly scaled floating gate NAND Flash memories is the cross-cell interference phenomenon. This is an active area of research in microelectronics engineering. In the last decade, there has been much progress and there are already proposed models for extraction of parasitic capacitive couplings within floating gate transistors. However, most of simulation-based methodologies for evaluation of the impact of cross-cell interference on the electrical behavior rely on deterministic capacitive coupling, neglecting the variability effects. This approach ignores the variable nature of the capacitive couplings caused by technological limitations such as line edge roughness (LER) in advanced technological nodes. The aim of this work is to present an alternative approach of modeling threshold voltage disturbance propagation in a raw NAND Flash memory array, sourced by variability-affected parasitic capacitive couplings. The major contribution of this work is the introduction of probabilistic framework to link the process technology and system level.