Abstract
A high density A mega bits DRAM (dynamic random access memory) which was named as FASIC (folded bit line adaptive side wall isolated capacitor cell) was made and reported in 1986. The cell has been fabricated on P-type Si single crystal substrate as four layers (one poly-Si, two poly-silicides and one Al layer) and has a size of 2.6μm × 4.2μm (one million cells in 2.6mm × 4.2mm).Figure 1 shows a light micrograph of a part of FASIC DRAM 6-inch wafer. The unit chip of the circuit in the wafer which is a square of 15mm × 15mm are shown by a circle A. The region indicated by B is the circuit for testing the memory cells and the ones indicated by C and D have 2M and AM memories in 7.5mm × 5mm and 15mm x 5mm respectively. AA' and BB' show two directions rectangular each other. Figure 2 shows schematically the cross-section along AA' direction, which parallel to bit line (BL). The cross sections of word line (WL), A1 line contact and trench (capacitor) are shown. The word line is vertical to bit line and parallel to BB' direction shown in Figure 1.
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