Cross-layer custom instruction selection to address PVTA variations and soft error

Abstract

•Process, Voltage, Temperature, and Aging (PVTA) variations introduce remarkable timing unpredictability to Custom Instructions (CIs) manufactured at nanoscale technology node. Moreover, shrinking the feature size to nanometer scales makes soft error another critical issue of CIs. To address these concerns, we propose a cross-layer CI selection methodology as a helping rein in the reliability decrease due to the combined effects of PVTA variations and soft error. According to this approach, in a top-down fashion, the information obtained at application and architecture levels is projected into device and circuit levels in order to accurately assess Soft Error Rate (SER) and the effects of the PVTA variations on the lifetimes and delays of CIs. Next, based on a bottom-up approach, timing information and SER of the underlying hardwares are captured at application-level CI selection merit functions. Experiments illustrate that our proposed cross-layer reliability-aware CI selection techniques extend the lifetime of the system up to 6.2×, while, SER is decreased by 2.5× on average.