Critical transistors nexus based circuit-level aging assessment and prediction

Abstract

Accurate age modeling, and fast, yet robust reliability sign-off emerged as mandatory constraints in Integrated Circuits (ICs) design for advanced process technology nodes. In this paper we introduce a novel method to assess and predict the circuit reliability at design time as well as at run-time. The main goal of our proposal is to allow for: (i) design time reliability optimization; (ii) fine tuning of the run-time reliability assessment infrastructure, and (iii) run-time aging assessment. To this end, we propose to select a minimum-size kernel of critical transistors and based on them to assess and predict an IC End-Of-Life (EOL) via two methods: (i) as the sum of the critical transistors end-of-life values, weighted by fixed topology-dependent coefficients, and (ii) by a Markovian framework applied to the critical transistors, which takes into account the joint effects of process, environmental, and temporal variations. The former model exploits the aging dependence on the circuit topology to enable fast run-time reliability assessment with minimum aging sensors requirements. By allowing the performance boundary to vary in time such that both remnant and nonremnant variations are encompassed, and imposing a Markovian evolution, the probabilistic model can be better fitted to various real conditions, thus enabling at design-time appropriate guardbands selection and effective aging mitigation/compensation techniques. The proposed framework has been validated for different stress conditions, under process variations and aging effects, for the ISCAS-85 c499 circuit, in PTM 45 nm technology. From the total of 1526 transistors, we obtained a kernel of 15 critical transistors, for which the set of topology dependent weights were derived. Our simulation results for 15 critical transistors kernel indicate a small approximation error (i.e., mean smaller than 15% and standard deviation smaller than 6%) for the considered circuit estimated end-of-life (EOL), when comparing to the end-of-life values obtained from Cadence simulation, which quantitatively confirm the accuracy of the IC lifetime evaluation. Moreover, as the number of critical transistors determines the area overhead, we also investigated the implications of reducing their number on the reliability assessment accuracy. When only 5 transistors are included into the critical set instead of 15, which results in a 66% area overhead reduction, the EOL estimation accuracy diminished with 18%. This indicates that area vs. accuracy trade-offs are possible, while maintaining the aging prediction accuracy within reasonable bounds.