Critical Bit Errors in CMOS Digital Inverters due to Pulsed Electromagnetic Interference

Abstract

The effects of pulsed electromagnetic interference (PEMI) on the operational parameters of digital CMOS inverters, is reported. The characteristics of 1.5 mum and 0.5 mum inverters were measured with and without pulsed interference with respect to the characteristics of the pulses, as power was varied between 0 and 24 dBm, at frequencies of 1 GHz and 3 GHz. New bit-flip (from V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OH</sub> to V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OL</sub> ) errors have been identified when the pulsed electromagnetic interference occurred at or below the threshold voltage of the MOSFET devices in the CMOS inverters. The bit-flip errors were observed to increase with narrower pulse widths and for the smaller devices, while for interference frequencies above 3 GHz, the power effects were found to be suppressed. The current transfer characteristics showed significant increase in the output current at the "ON" and "OFF" states of the inverters, which is found to be a critical vulnerability leading to catastrophic device failure due to metallization and interconnect failure. The comparison between measured current transfer characteristics of the 1.5 mum and 0.5 mum CMOS inverters under pulsed and CW interference and empirical channel mobility model showed that the observed output current increase had a weak dependence on thermal effects, suggesting that the electromagnetic interference effects are predominantly excess charge related.